The present invention relates to a Static Induction Transistor Logic (hereinafter referred to as SITL) device and an Integrated Injection Logic (hereinafter referred to as IIL) device which are constructed with a lamination circuit construction respectively and can be operated with less power consumption than prior art devices.
Among the many semiconductor devices, a SITL semiconductor device and a IIL semiconductor device are the semiconductor devices which can be operated at high frequency and with less power consumption, that is, in which the delay-power products thereof are small and the packing densities thereof are high.
The SITL semiconductor device consists of a lateral PNP transistor which acts as an injector and a longitudinal field effect transistor which acts as a driving transistor. On the other hand the IIL semiconductor device consists of a lateral PNP transistor which acts as an injector and a longitudinal NPN transistor which acts as a driving transistor.
In the SITL semiconductor device and IIL semiconductor device a lamination circuit construction is sometimes used in order to make it to operate with a small logical-amplitude-level (such as 0.7 volts) and to effectively use an injection current. For example, when a double-layer construction is used, it is required to exchange the signal between the upper layer and the lower layer by using a signal-level converting circuit. When the signal is converted from the upper layer to the lower layer, in the prior art, the collector of the transistor for converting the signal level is directly connected to the gate of the longitudinal field effect driving transistor or to the base of the longitudinal NPN driving transistor formed in the respective lower layers, so large injection currents flow.